VLSI implementation of MIMO detection using the sphere decoding algorithm

Authors

Andreas Burg, Moritz Borgmann, Markus Wenk, Martin Zellweger, Wolfgang Fichtner, and Helmut Bölcskei

Reference

IEEE Journal of Solid-State Circuits, Vol 40, No. 7, pp. 1566-1577, July 2005, (invited paper)

DOI: 10.1109/JSSC.2005.847505

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Abstract

Multiple-input multiple-output (MIMO) techniques are a key enabling technology for high-rate wireless communications. This paper discusses two ASIC implementations of MIMO sphere decoders. The first ASIC attains maximum-likelihood performance with an average throughput of 73 Mbps at a signal-to-noise ratio (SNR) of 20 dB; the second ASIC shows only a negligible bit error rate degradation and achieves a throughput of 170 Mbps at the same SNR. The three key contributing factors to high throughput and low complexity are: Depth-first tree traversal with radius reduction, implemented in a one-node-per-cycle architecture, the use of the l-infinity- instead of l-2-norm, and finally the efficient implementation of the enumeration approach recently proposed in [1]. The resulting ASICs currently rank among the fastest reported MIMO detector implementations.

Keywords

Detection, maximum likelihood (ML), multiple-input multiple-output (MIMO), spatial multiplexing, sphere decoding, very large scale integration (VLSI), wireless communications

Correction: The scaling behavior of the infinity-norm discussed at the end of Sec.IV.B was corrected to \sqrt{\log M_{T}}.


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