Studien-/ Diplomarbeit

FPGA: Design and Implementation of a Space-Time Decoder

Supporting high data rates for broadband (multimedia-) data access will be important for future wireless communication systems. The use of multiple transmit and/or receive antennas (MIMO = multiple input multiple output) make those high data rates on a rich-scattering wireless channel possible. One basic transmission technique for these systems is called spatial multiplexing which increases spectral efficiency. The idea of spatial multiplexing is to "break up" the data stream into several parallel data streams, which are then transmitted simultaneously from the transmit antennas. Each receive antenna observes a superposition of these transmitted data streams. Thus the received signal is affected by intersymbol interference (ISI), which makes the use of an equalizer necessary.

Several ISI compensation methods can be applied for example MMSE (minimum mean squared error) equalization or parallel or serial ISI cancellation. Recently the Wireless Communication Group of the Communication Technology Laboratory developed a very flexible and efficient equalizer [1]. This decision feedback equalizer (DFE) achieves almost the performance of the maximum likelihood (ML) decoder but with much lower computational complexity.

In this project the DFE (decision feedback equalizer) proposed in [1] should be implemented on a FPGA device. The aim is first to convert the available MATLAB code, which uses floating point arithmetic into a fixed point representation. A further goal is to determine reduced complexity matrix inversion algorithms used by the DFE. Finally the DFE should be implemented and tested on a FPGA.

[1] M. Kuhn, A. Wittneben, "A new scalable decoder for linear block codes with intersymbol interference", Proc. VTC, May 2002.

Subject area Hardware Implementation, Space-Time Processing, Signal Processing, FPGA
Type of work 50% Hardware, 25% Theory, 25% Simulation
Supervisor Dr. Boris Rankov
Professor Prof. Dr. Armin Wittneben